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| ? semiconductor components industries, llc, 2015 april, 2015 ? rev. 3 1 publication order number: NCL30085/d NCL30085 power factor corrected quasi-resonant primary side current-mode controller for led lighting with line step dimming and thermal foldback the NCL30085 is a power factor corrected flyback controller targeting isolated and non?isolated constant current led drivers. the controller operates in a quasi?resonant mode to provide optimal efficiency. thanks to a novel control method, the device is able to tightly regulate a constant led current from the primary side. this removes the need for secondary side feedback circuitry, biasing and an optocoupler. the device is highly integrated with a minimum number of external components. a robust suite of safety protection is built in to simplify the design. this device is specifically intended for very compact, space efficient designs and supports 3 levels of log step dimming which allows light output reduction by toggling the main ac switch on and off to signal the controller to reduce the led current point down to 5% of full load. features ? quasi?resonant peak current?mode control operation ? constant current control with primary side feedback ? tight led constant current regulation of 2% typical ? power factor correction ? 3 step dimming (70/25/5%) ? line feedforward for enhanced regulation accuracy ? low start?up current (10 a typ.) ? wide v cc range ? 300 ma / 500 ma totem pole driver with 12 v gate clamp ? robust protection features ? ovp on v cc ? programmable over voltage / led open circuit protection ? cycle?by?cycle peak current limit ? winding short circuit protection ? secondary diode short protection ? output short circuit protection ? current sense short protection ? user programmable ntc based thermal foldback ? thermal shutdown ? v cc undervoltage lockout ? brown?out protection ? pb?free, halide?free msl1 product typical applications ? integral led bulbs and tubes ? led light engines ? led drivers/power supplies www. onsemi.com soic?8 nb case 751 pin connections marking diagram (top view) l30085x = specific device code x = a, b a = assembly location l = wafer lot y = year w = work week = pb-free package see detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. ordering information v cc drv gnd 1 cs vs comp zcd sd 1 8 l30085x alyw 1 8
NCL30085 www. onsemi.com 2 1 2 3 45 8 6 7 . . aux . NCL30085 sense r figure 1. typical application schematic for NCL30085 table 1. pin function description pin no pin name function pin description 1 zcd zero crossing detection connected to the auxiliary winding, this pin detects the core reset event. 2 vs input voltage sensing this pin observes the input voltage rail and protects the led driver in case of too low mains conditions (brown?out). this pin also observes the input voltage rail for: ? power factor correction ? valley lockout ? step dimming 3 comp filtering capacitor this pin receives a filtering capacitor for power factor correction. typical values ranges from 1 ? 4.70 f 4 sd thermal foldback and shutdown connecting an ntc to this pin allows the user to program thermal current fold- back threshold and slope. a zener diode can also be used to pull?up the pin and stop the controller for adjustable ovp protection. 5 cs current sense this pin monitors the primary peak current. 6 gnd ? controller ground pin. 7 drv driver output the driver?s output to an external mosfet 8 v cc ic supply pin this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 18 v and turns off when v cc goes below 8.8 v (typical values). after start?up, the operating range is 9.4 v up to 26 v ( v cc ( ovp ) minimum level). NCL30085 www. onsemi.com 3 internal circuit architecture sd thermal foldback over temp. protection over voltage protection zcd zero crossing detection logic (zcd blanking, time?out, ...) valley selection cs power factor and constant?current control leading edge blanking winding and output diode short circuit protection max. peak current limit ipkmax wod_scp drv vcc management vcc drv vcc over voltage protection vcc internal thermal shutdown (auto?recovery or latched) fault management clamp circuit vs brown?out bo_nok s r q q cs_reset stop uvlo off latch stop wod_scp bo_nok gnd stop aux. winding short circuit prot. aux_scp aux_scp vcc_max ff_mode v line feed?forward vs v vs ipkmax v tf v tf v ref v dd v ref v vs enable cs short protection cs_ok cs_ok v ref frequency foldback ff_mode step_dim maximum on time refx v refx v uvlo on,max t on,max t dimming control v vs refx v comp figure 2. internal circuit architecture (auto?recovery or latched) NCL30085 www. onsemi.com 4 table 2. maximum ratings table symbol rating value unit v cc(max) i cc(max) maximum power supply voltage, v cc pin, continuous voltage maximum current for v cc pin ?0.3 to 30 internally limited v ma v drv(max) i drv(max) maximum driver pin voltage, drv pin, continuous voltage maximum current for drv pin ?0.3, v drv (note 1) ?300, +500 v ma v max i max maximum voltage on low power pins (except drv and v cc pins) current range for low power pins (except drv and v cc pins) ?0.3, 5.5 (notes 2 and 5) ?2, +5 v ma r j?a thermal resistance junction?to?air 180 c/w t j(max) maximum junction temperature 150 c operating temperature range ?40 to +125 c storage temperature range ?60 to +150 c esd capability, hbm model (note 3) 3.5 kv esd capability, mm model (note 3) 250 v esd capability, cdm model (note 3) 2 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. v drv is the drv clamp voltage v drv(high) when v cc is higher than v drv(high) . v drv is v cc otherwise. 2. this level is low enough to guarantee not to exceed the internal esd diode and 5.5?v zener diode. more positive and negative voltage s can be applied if the pin current stays within the ?2?ma / 5?ma range. 3. this device contains esd protection and exceeds the following tests: human body model 3500 v per jedec st andard jesd22?a114e, machine model method 250 v per jedec standard jesd22?a115b, c harged device model 2000 v per jedec standard jesd22?c101e. 4. this device contains latch?up protection and has been tested per jedec standard jesd78d, class i and exceeds 100 ma 5. recommended maximum v s voltage for optimal operation is 4 v. ?0.3 v to +4.0 v is hence, the v s pin recommended range. table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v cs = 0 v, v sd = 1.5 v) for min/max values t j = ?40 c to +125 c, v cc = 12 v) description test condition symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage hysteresis v cc(on) ? v cc(off) internal logic reset v cc rising v cc rising v cc falling v cc(on) v cc(off) v cc(hys) v cc(reset) 16.0 8.2 8 4 18.0 8.8 ? 5 20.0 9.4 ? 6 v v cc over voltage protection threshold v cc(ovp) 25.5 26.8 28.5 v v cc(off) noise filter v cc(reset) noise filter t vcc(off) t vcc(reset) ? ? 5 20 ? ? s startup current i cc(start) ? 13 30 a startup current in fault mode i cc(s fault) 58 75 a supply current device disabled/fault device enabled/no output load on pin 7 device switching (f sw = 65 khz) v cc > v cc(off) f sw = 65 khz c drv = 470 pf, f sw = 65 khz i cc1 i cc2 i cc3 0.8 ? ? 1.0 2.5 3.0 1.2 4.0 4.5 ma current sense maximum internal current limit v ilim 0.95 1.00 1.05 v leading edge blanking duration for v ilim t leb 240 300 360 ns line feed?forward current drv high, v vs = 2 v i ff 35 40 45 a 6. guaranteed by design 7. a ntc is generally placed between the sd and gnd pins. parameters r tf(start) , r tf(stop) , r otp(off) and r otp(on) give the resistance the ntc must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the otp limit and allow the circuit re covery after an otp situation. 8. at startup, when v cc reaches v cc(on) , the controller blanks otp for more than 250 s to avoid detecting an otp fault by allowing the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. NCL30085 www. onsemi.com 5 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v cs = 0 v, v sd = 1.5 v) for min/max values t j = ?40 c to +125 c, v cc = 12 v) description unit max typ min symbol test condition current sense propagation delay from current detection to gate off?state t ilim ? 100 150 ns maximum on?time t on(max) 26 36 46 s threshold for immediate fault protection activation v cs(stop) 1.35 1.50 1.65 v leading edge blanking duration for v cs(stop) t bcs ? 150 ? ns current source for cs to gnd short detection i cs(short) 400 500 600 a current sense threshold for cs to gnd short de- tection v cs rising v cs(low) 30 65 100 mv gate drive drive resistance drv sink drv source r snk r src ? ? 13 30 ? ? drive current capability drv sink (note 6) drv source (note 6) i snk i src ? ? 500 300 ? ? ma rise time (10% to 90%) c drv = 470 pf t r ? 40 ? ns fall time (90% to 10%) c drv = 470 pf t f ? 30 ? ns drv low voltage v cc = v cc(off) +0.2 v c drv = 470 pf, r drv =33 k v drv(low) 8 ? ? v drv high voltage v cc = v cc(max) c drv = 470 pf, r drv =33 k v drv(high) 10 12 14 v zero voltage detection circuit upper zcd threshold voltage v zcd rising v zcd(rising) ? 90 150 mv lower zcd threshold voltage v zcd falling v zcd(falling) 35 55 ? mv zcd hysteresis v zcd(hys) 15 ? ? mv propagation delay from valley detection to drv high v zcd falling t dem ? 100 300 ns blanking delay after on?time v refx > 30% v ref t zcd(blank1) 1.12 1.50 1.88 s blanking delay at light load v refx < 25% v ref t zcd(blank2) 0.56 0.75 0.94 s timeout after last demag transition t timo 5.0 6.5 8.0 s pulling?down resistor v zcd = v zcd(falling) r zcd(pd) ? 200 ? k constant current and power factor control reference voltage at t j = 25 c v ref 245 250 255 mv reference voltage t j = 25 c to 100 c v ref 242.5 250.0 257.5 mv reference voltage t j = ?40 c to 125 c v ref 240 250 260 mv current sense lower threshold v cs falling v cs(low) 20 50 100 mv v control to current setpoint division ratio v ratio ? 4 ? ? error amplifier gain v refx =v ref (no dimming) v refx =25%* v ref g ea 40 50 200 60 s 6. guaranteed by design 7. a ntc is generally placed between the sd and gnd pins. parameters r tf(start) , r tf(stop) , r otp(off) and r otp(on) give the resistance the ntc must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the otp limit and allow the circuit re covery after an otp situation. 8. at startup, when v cc reaches v cc(on) , the controller blanks otp for more than 250 s to avoid detecting an otp fault by allowing the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. NCL30085 www. onsemi.com 6 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v cs = 0 v, v sd = 1.5 v) for min/max values t j = ?40 c to +125 c, v cc = 12 v) description unit max typ min symbol test condition constant current and power factor control error amplifier current capability v refx =v ref (no dimming) v refx =25%* v ref i ea 60 240 a comp pin start?up current source no dimming, comp pin grounded i ea_stup 140 a line feed forward v vs to i cs(offset) conversion ratio k lff 18 20 22 s line feed?forward current on cs pin drv high, v vs = 2 v i ff 35 40 45 a offset current maximum value v vs > 5 v i offset(max) 80 100 120 a valley lockout section threshold for high? line range (hl) detection v vs rising v hl 2.28 2.40 2.52 v threshold for low?line range (ll) detection v vs falling v ll 2.18 2.30 2.42 v blanking time for line range detection t hl(blank) 15 25 35 ms valley lockout first step valley in high?line. second step valley in high?line. third step valley in high?line. first step valley in low?line. second step valley in low?line. third step valley in low?line. v hl100% v hl70% v hl25% v ll100% v ll70% v ll25% 2 3 6 1 2 5 frequency foldback additional dead time v refx = 25%*v ref t ff1ll 1.4 2.0 2.6 s additional dead time v refx = 5%*v ref t ff2hl ? 40 ? s fault protection thermal shutdown (note 6) f sw = 65 khz t shdn 130 150 170 c thermal shutdown hysteresis t shdn(hys) ? 50 ? c threshold voltage for output short circuit or aux. winding short circuit detection v zcd(short) 0.8 1.0 1.2 v short circuit detection timer v zcd < v zcd(short) t ovld 70 90 110 ms auto?recovery timer duration t recovery 3 4 5 s sd pin clamp series resistor r sd(clamp) 1.6 k clamped voltage sd pin open v sd(clamp) 1.13 1.35 1.57 v sd pin detection level for ovp v sd rising v ovp 2.35 2.50 2.65 v delay before ovp or otp confirmation (ovp and otp) t sd(delay) 22.5 30.0 37.5 s reference current for direct connection of an ntc (note 8) i otp(ref) 80 85 90 a fault detection level for otp (note 7) v sd falling v otp(off) 0.47 0.50 0.53 v sd pin level for operation recovery after an otp detection v sd rising v otp(on) 0.66 0.70 0.74 v 6. guaranteed by design 7. a ntc is generally placed between the sd and gnd pins. parameters r tf(start) , r tf(stop) , r otp(off) and r otp(on) give the resistance the ntc must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the otp limit and allow the circuit re covery after an otp situation. 8. at startup, when v cc reaches v cc(on) , the controller blanks otp for more than 250 s to avoid detecting an otp fault by allowing the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. NCL30085 www. onsemi.com 7 table 3. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v cs = 0 v, v sd = 1.5 v) for min/max values t j = ?40 c to +125 c, v cc = 12 v) description unit max typ min symbol test condition fault protection otp blanking time when circuit starts operating (note 8) t otp(start) 250 370 s sd pin voltage at which thermal fold?back starts (v ref is decreased) v tf(start) 0.94 1.00 1.06 v sd pin voltage at which thermal fold?back stops (v ref is clamped to v ref50 ) v tf(stop) 0.64 0.69 0.74 v v tf(start) over i otp(ref) ratio (note 7) t j = +25 c to +125 c r tf(start) 10.8 11.7 12.6 k v tf(stop) over i otp(ref) ratio (note 7) t j = +25 c to +125 c r tf(stop) 7.4 8.1 8.8 k v otp(off) over i otp(ref) ratio (note 7) t j = +25 c to +125 c r otp(off) 5.4 5.9 6.4 k v otp(on) over i otp(ref) ratio (note 7) t j = +25 c to +125 c r otp(on) 7.5 8.1 8.7 k v refx @ v sd = 600 mv (percent of v ref ) sd pin falling, no otp detection v ref(50) 40 50 60 % brown?out brown?out on level (ic start pulsing) v s rising v bo(on) 0.95 1.00 1.05 v brown?out off level (ic shuts down) v s falling v bo(off) 0.85 0.90 0.95 v bo comparators delay t bo(delay) 30 s brown?out blanking time t bo(blank) 15 25 35 ms v s pin pulling?down current v s = v bo(on) i bo(bias) 50 250 450 na step dimming reset time v s < v bo(off) t step?reset 2.4 3.2 4.0 s 6. guaranteed by design 7. a ntc is generally placed between the sd and gnd pins. parameters r tf(start) , r tf(stop) , r otp(off) and r otp(on) give the resistance the ntc must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the otp limit and allow the circuit re covery after an otp situation. 8. at startup, when v cc reaches v cc(on) , the controller blanks otp for more than 250 s to avoid detecting an otp fault by allowing the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. NCL30085 www. onsemi.com 8 typical characteristics figure 3. v cc start?up threshold vs. temperature figure 4. v cc minimum operating voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 16.0 16.5 17.0 17.5 18.0 19.0 19.5 20.0 125 100 75 50 25 0 ?25 ?50 8.2 8.3 8.5 8.7 8.9 9.0 9.2 9.4 figure 5. hysteresis (v cc(on) ? v cc(off) ) vs. temperature figure 6. v cc(reset) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 7.5 8.0 8.5 9.0 9.5 10.5 11.0 11.5 125 100 75 50 25 0 ?25 ?50 4.0 4.2 4.6 4.8 5.0 5.4 5.8 6.0 v cc(on) (v) v cc(off) (v) v cc(hys) (v) v cc(reset) (v) 150 18.5 150 8.4 8.6 8.8 9.1 9.3 150 10.0 150 4.4 5.2 5.6 NCL30085 www. onsemi.com 9 typical characteristics figure 7. v cc over voltage protection threshold vs. temperature figure 8. start?up current vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 25.6 26.0 26.2 26.6 27.0 27.4 27.6 28.0 125 100 75 50 25 0 ?25 ?50 0 5 10 15 20 30 35 40 figure 9. start?up current in fault mode vs. temperature figure 10. i cc1 vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 25 50 75 100 125 150 125 100 75 50 25 0 ?25 ?50 0.4 0.6 0.8 1.0 1.2 1.6 1.8 2.0 figure 11. i cc2 vs. temperature figure 12. i cc3 vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 1.2 1.6 2.0 2.4 2.6 3.0 3.4 3.8 125 100 75 50 25 0 ?25 ?50 1.0 1.5 2.0 2.5 3.0 4.0 4.5 5.0 v cc(ovp) (v) i cc(start) ( a) i cc(sfault) ( a) i cc1 (ma) i cc2 (ma) i cc3 (ma) 150 25.8 26.4 26.8 27.2 27.8 150 25 150 150 1.4 150 1.4 1.8 2.2 2.8 3.2 3.6 150 3.5 NCL30085 www. onsemi.com 10 typical characteristics figure 13. maximum internal current limit vs. temperature figure 14. leading edge blanking vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.95 0.97 0.98 1.00 1.03 1.05 125 100 75 50 25 0 ?25 ?50 200 220 240 260 280 320 340 400 figure 15. current limit propagation delay vs. temperature figure 16. maximum on?time vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 10 50 70 100 120 150 125 100 75 50 25 0 ?25 ?50 30 32 34 38 40 44 48 50 figure 17. v cs(stop) vs. temperature figure 18. leading edge blanking duration for v cs(stop) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 1.38 1.42 1.46 1.48 1.50 1.54 1.60 125 100 75 50 25 0 ?25 ?50 100 110 130 140 170 210 220 v ilim (v) t leb (ns) t ilim (ns) t on(max) ( s) v cs(stop) (v) t bcs (ns) 150 0.96 0.99 1.01 1.02 1.04 150 300 150 150 42 150 1.40 1.44 1.52 1.58 150 180 360 380 20 30 40 60 80 90 110 130 140 36 46 1.56 120 150 190 160 200 NCL30085 www. onsemi.com 11 typical characteristics figure 19. i cs(short) vs. temperature figure 20. v cs(low) , v cs rising vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 400 420 440 480 540 560 600 125 100 75 50 25 0 ?25 ?50 20 30 40 50 60 80 90 100 figure 21. sink gate drive resistance vs. temperature figure 22. source gate drive resistance vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 2 6 10 12 16 20 125 100 75 50 25 0 ?25 ?50 10 14 16 20 24 32 36 40 figure 23. gate drive rise time vs. temperature figure 24. gate drive fall time (c drv = 470 pf) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 15 25 35 40 50 125 100 75 50 25 0 ?25 ?50 0 5 10 20 25 40 45 50 i cs(short) ( a) v cs(low) (mv) r snk ( ) r src ( ) t r (ns) t f (ns) 150 460 500 520 580 150 70 150 150 28 150 5 10 20 30 45 150 30 4 8 14 18 12 18 22 26 30 34 38 15 35 NCL30085 www. onsemi.com 12 typical characteristics figure 25. drv low voltage vs. temperature figure 26. drv high voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 8.2 8.4 8.6 8.8 9.4 9.8 125 100 75 50 25 0 ?25 ?50 10.0 10.5 11.0 12.0 12.5 13.5 14.5 15.0 figure 27. upper zcd threshold voltage vs. temperature figure 28. lower zcd threshold vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 30 50 70 90 100 130 150 125 100 75 50 25 0 ?25 ?50 30 35 40 50 55 70 75 80 figure 29. zcd hysteresis vs. temperature figure 30. zcd blanking delay vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 5 15 25 35 40 50 125 100 75 50 25 0 ?25 ?50 1.0 1.1 1.2 1.4 1.5 1.7 1.9 2.0 v drv(low) (v) v drv(high) (v) v zcd(rising) (mv) v zcd(falling) (mv) v zcd(hys) (mv) t zcd(blank1) ( s) 150 9.0 9.2 9.6 150 13.0 150 150 60 150 10 20 30 45 150 1.6 11.5 14.0 40 60 80 110 120 140 45 65 1.3 1.8 NCL30085 www. onsemi.com 13 typical characteristics figure 31. zcd time?out vs. temperature figure 32. reference voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 5.8 6.2 6.6 7.0 7.2 7.4 7.8 125 100 75 50 25 0 ?25 ?50 244 245 247 248 250 253 254 256 figure 33. current sense lower threshold (v cs falling) vs. temperature figure 34. error amplifier trans?conductance gain vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 10 20 40 60 80 90 110 125 100 75 50 25 0 ?25 ?50 42 44 46 48 50 56 58 60 figure 35. feedforward v vs to i cs(offset) conversion ratio vs. temperature figure 36. line feedforward current on cs pin (@ v vs = 2 v) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 18.0 18.5 19.0 20.0 21.5 22.0 125 100 75 50 25 0 ?25 ?50 36 37 38 39 40 42 43 44 t timo ( s) v ref (mv) v cs(low) (mv) g ea ( s) k lff ( s) i ff ( a) 150 6.0 6.4 6.8 7.6 150 251 150 150 54 150 19.5 20.5 21.0 150 41 246 249 252 255 30 50 70 100 52 NCL30085 www. onsemi.com 14 typical characteristics figure 37. i offset(max) vs. temperature figure 38. threshold for high?line range detection vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 80 85 90 95 110 120 125 100 75 50 25 0 ?25 ?50 2.25 2.30 2.35 2.40 2.50 2.55 figure 39. threshold for low?line range detection vs. temperature figure 40. blanking time for low?line range detection vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 2.20 2.25 2.35 2.40 2.50 2.55 2.60 125 100 75 50 25 0 ?25 ?50 20 22 24 28 30 34 38 40 figure 41. threshold voltage for output short circuit detection vs. temperature figure 42. short circuit detection timer vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.80 0.85 1.00 1.15 1.20 125 100 75 50 25 0 ?25 ?50 75 80 85 90 95 105 110 115 i offset(max) ( a) v hl (v) v ll (v) t hl(blank) (ms) v zcd(short) (v) t ovld (ms) 150 100 105 115 150 2.45 150 150 32 150 0.90 0.95 1.05 1.10 150 100 2.30 2.45 26 36 NCL30085 www. onsemi.com 15 typical characteristics figure 43. auto?recovery timer duration vs. temperature figure 44. sd pin clamp series resistor vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 3.00 3.25 3.50 3.75 4.50 5.00 125 100 75 50 25 0 ?25 ?50 1.00 1.10 1.30 1.40 1.60 1.90 2.00 2.20 figure 45. sd pin clamp voltage vs. temperature figure 46. sd pin ovp threshold voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 1.10 1.15 1.30 1.35 1.45 1.50 1.60 125 100 75 50 25 0 ?25 ?50 2.40 2.42 2.44 2.46 2.50 2.54 2.56 2.58 figure 47. t sd(delay) vs. temperature figure 48. i otp(ref) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 22 24 30 38 125 100 75 50 25 0 ?25 ?50 79 80 82 83 85 88 89 91 t recovery (s) r sd(clamp) (k ) v sd(clamp) (v) v ovp (v) t sd(delay) ( s) i otp(ref) ( a) 150 4.00 4.25 4.75 150 1.70 150 150 2.52 150 26 28 32 34 36 150 86 1.20 1.50 1.80 2.10 1.20 1.25 1.40 1.55 2.48 81 84 87 90 NCL30085 www. onsemi.com 16 typical characteristics figure 49. r tf(start) vs. temperature figure 50. r tf(stop) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 11.0 11.2 11.3 11.6 11.9 12.1 12.2 12.5 125 100 75 50 25 0 ?25 ?50 7.6 7.7 7.9 8.0 8.2 8.5 8.7 8.8 figure 51. r otp(off) vs. temperature figure 52. r otp(on) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 5.4 5.5 5.7 5.9 6.0 6.3 6.4 125 100 75 50 25 0 ?25 ?50 7.6 7.7 7.9 8.0 8.2 8.5 8.6 8.8 figure 53. ratio v ref(50) over v ref vs. temperature figure 54. brown?out on level vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 45 48 50 52 53 55 125 100 75 50 25 0 ?25 ?50 0.95 0.96 0.97 0.98 0.99 1.03 1.04 1.05 r tf(start) (k ) r tf(stop) (k ) r otp(off) (k ) r otp(on) (k ) v ref(50) (%) v bo(on) (v) 150 11.1 11.5 11.7 12.0 12.4 150 8.3 150 150 8.4 150 46 47 49 51 54 150 1.01 11.4 11.8 12.3 7.8 8.1 8.4 8.6 5.6 5.8 6.1 6.2 7.8 8.1 8.3 8.7 1.00 1.02 NCL30085 www. onsemi.com 17 typical characteristics figure 55. brown?out off level vs. temperature figure 56. brown?out blanking time vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.85 0.86 0.87 0.89 0.91 0.92 0.93 0.95 125 100 75 50 25 0 ?25 ?50 20 22 24 25 27 31 33 35 figure 57. v s pin pulling?down current vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 50 200 250 300 400 500 v bo(off) (v) t bo(blank) (ms) i bo(bias) (na) 150 0.88 0.90 0.94 150 29 150 21 23 26 28 30 32 34 100 150 350 450 NCL30085 www. onsemi.com 18 application information the NCL30085 is a driver for power?factor corrected flyback and non?isolated buck?boost and sepic converters. it implements a current?mode, quasi?resonant architecture including valley lockout and frequency fold?back capabilities for maintaining high?efficiency performance over a wide load range. a proprietary circuitry ensures both accurate regulation of the output current (without the need for a secondary?side feedback) and near?unity power factor correction. the circuit contains a suite of powerful protections to ensure a robust led driver design without the need for extra external components or overdesign. ? quasi?resonance curr ent?mode operation: implementing quasi?resonance operation in peak current?mode control, the NCL30085 optimizes the efficiency by turning on the mosfet when its drain?source voltage is minimal (valley). in light?load conditions, the circuit changes valleys to reduce the switching losses. for stable operation, the valley at which the mosfet switches on remains locked until the input voltage or the output current set?point significantly changes. ? primary?side constant?current control with power factor correction: a proprietary circuitry allows the led driver to achieve both near?unity power factor correction and accurate regulation of the output current without requiring any secondary?side feedback (no optocoupler needed). a power factor as high as 0.99 and an output current deviation below 2% are typically obtained. ? step dimming: the step dimming function decreases the output current from 100% to 5% of its nominal value in 3 discrete steps. whenever a brown?out is detected, the output current is decreased by reducing the reference voltage v ref . the step?dimming function is reset if the v s pin remains below the lower brown?out threshold (v bo(off) ) for more than 3 s typically. ? main protection features: ? over temperature thermal fold?back / shutdown/ over voltage protection: the NCL30085 features a gradual current foldback to protect the driver from excessive temperature down to 50% of the programmed current. this represents a power reduction of the led by more than 50%. if the temperature continues to rise after this point to a second level, the controller stops operating. this mode would only be expected to be reached if there is a severe fault. the first and second temperature thresholds depend on the value of the ntc connected to the sd pin. note, the sd pin can also be used to shutdown the device by pulling this pin below the v otp(off) min level . a zener diode can also be used to pull?up the pin and stop the controller for adjustable ovp protection. both protections are latching?off (a version) or auto?recovery (the circuit can recover operation after 4?s delay has elapsed ? b version). ? cycle?by?cycle peak curr ent limit: when the current sense voltage exceeds the internal threshold v ilim , the mosfet is immediately turned off for that switch cycle. ? winding or output diode short?circuit protection: an additional comparator senses the cs signal and stops the controller if it exceeds 150% x v ilim for 4 consecutive cycles. this feature can protect the converter if a winding is shorted or if the output diode is shorted or simply if the transformer saturates. this protection is latching?off (a version) or auto?recovery (b version). ? output short?circuit protection: if the zcd pin voltage remains low for a 90?ms time interval, the controller detects that the output or the zcd pin is grounded and hence, stops operation. this protection is latching?off (a version) or auto?recovery (b version). ? open led protection: if the v cc pin voltage exceeds the ovp threshold, the controller shuts down and waits 4 seconds before restarting switching operation. ? floating or short pin detection: the circuit can detect most of these situations which helps pass safety tests. power factor and constant current control the NCL30085 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the zcd, v s and cs pin voltages (signals zcd, v vs and v cs of figure 58). this circuitry generates the current setpoint (v control /4) and compares it to the current sense signal (v cs ) to dictate the mosfet turning off event when v cs exceeds v control /4. NCL30085 www. onsemi.com 19 power factor and constant?current control pwm latch reset stop v vs refx v comp zcd c1 cs v figure 58. power factor and constant?current control as illustrated in figure 58, the v s pin provides the sinusoidal reference necessary for shaping the input current. the obtained current reference is further modulated so that when averaged over a half?line period, it is equal to the output current reference (v refx ). this averaging process is made by an internal operational trans?conductance amplifier (ot a) and the capacitor connected to the comp pin (c1 of figure 58). typical comp capacitance is 1 f and should not be less than 470 nf to ensure stability. the comp ripple does not affect the power factor performance as the circuit digitally eliminates it when generating the current setpoint. if the v s pin properly conveys the sinusoidal shape, power factor will be close to unity and the total harmonic distortion (thd) will be low. in any case, the output current will be well regulated following the equation below: i out v refx 2n ps r sense (eq. 1) where: ? n ps is the secondary to primary transformer turns n ps = n s /n p ? r sense is the current sense resistor (see figure 1). ? v refx is the output current internal reference. v refx = v ref (250 mv typically) at full load. the output current reference (v refx ) is 250 mv typically (v ref ). in the event that step dimming is engaged, v refx takes a lower value based on the step?dimming level (see ?step dimming? section) or if the temperature is high enough to activate the thermal fold?back (see ?protections? section). if a major fault is detected, the circuit enters the latched?off or auto?recovery mode and the comp pin is grounded (except in an uvlo condition). this ensures a clean start?up when the circuit resumes operation. start?up sequence generally an led lamp is expected to emit light in < 1 sec and typically within 300 ms. the start?up phase consists of the time to charge the v cc capacitor, initiate startup and begin switching and the time to charge the output capacitor until sufficient current flows into the led string. to speed?up this phase, the following defines the start?up sequence: ? the comp pin is grounded when the circuit is off. the average comp voltage needs to exceed the v s pin peak value to have the led current properly regulated (whatever the current target is). to speed?up the comp capacitance charge and shorten the start?up phase, an internal 80? a current source adds to the ota sourced current (60 a max typically) to charge up the comp capacitance. the 80? a current source remains on until the ota starts to sink current as a result of the comp pin voltage sufficient rise. at that moment, the comp pin being near its steady?state value, it is only driven by the ota. ? whatever the step?dimming state is, the output current reference is set maximum (v refx = v ref ) until the zcd pin voltage reaches the 1?v v zcd(short) threshold. this prevents the circuit from detecting an output short (aux_scp protection trips if the zcd pin voltage does not exceed 1?v v zcd(short) threshold within a 90?ms delay) just because dimming would make the output voltage charge up slowly. if the system cannot start?up in one v cc cycle, the aux_scp 90?ms blanking time is not reset and v refx remains maximum for all the necessary v cc cycles until the zcd pin voltage reaches the 1?v v zcd(short) threshold. ? if v cc drops below the v cc(off) threshold because the circuit fails to start?up properly on the first attempt, a new try takes place as soon as v cc is recharged to v cc(on) . the comp voltage is not reset at that moment. instead, the new attempt starts with the comp level obtained at the end of the previous operating phase. ? if the load is shorted, the circuit will operate in hiccup mode with v cc oscillating between v cc(off) and v cc(on) until the aux_scp protection trips (aux_scp is triggered if the zcd pin voltage does not exceed 1 v within a 90?ms operation period of time thus indicating a short to ground of the zcd pin or an excessive load preventing the output voltage from rising). the NCL30085a latches off in this case. with the b version, the aux_scp protection forces the 4?s auto?recovery delay to reduce the operation duty?ratio. figure 59 illustrates a start?up sequence with the output shorted to ground, in this second case. NCL30085 www. onsemi.com 20 cc(on) v cc(off) v () 4 recovery ts () 1 t 2 t 3 t () 123 90 ovld ovld aux_scptrips as t t t tms + 1 t 2 t 3 t () 4 recovery ts () cc v drv time time figure 59. start?up sequence in a load short?circuit situation (auto?recovery version) t += step dimming the step dimming function decreases the output current from 100% to 5% of its nominal value in 3 discrete steps. the table below shows the different steps value and the corresponding reference voltage value. each time a brown?out is detected, the output current is decreased by decreasing the reference voltage v ref . a counter is incremented by the bo_nok (brown?out not ok) signal and selects one of the four corresponding reference thresholds: v ref , v ref70, v ref25 , v ref5 . after counting up to 4, the counter is reset. table 4. dimming steps dimming step iout on 100% 1 70% 2 25% 3 5% note : the step dimming state is memorized until v cc crosses v cc ( reset ) or v vs is below v bo(off) for 3 s (typical). the circuit consumption is optimized (in particular, it equals i cc ( fault ) when v cc is lower than v cc ( off ) ) so that the v cc voltage does not drop too fast for the step dimming brown?out event. the power supply designer should use a split v cc circuit as shown in figure 60 where a small capacitor c 1 is used for a fast start?up while a larger c 2 capacitance provides the necessary storage capability for step dimming. during step dimming, at startup, the controller generates the first drv pulses after 1 time?out pulse even if a higher valley number is selected by v refx . this avoids long startup time while dimming at low output current value. vcc c 1 c 2 figure 60. split v cc supply the step?dimming function is reset if the v s pin is maintained below the v bo(off) brown?out threshold for the t step_reset time. t step_reset is 3 s typically. in other words, any brown?out event that is longer than t step_reset , leads the controller to re?start at 100% current setting. zero crossing detection block the zcd pin detects when the drain?source voltage of the power mosfet reaches a valley by crossing below the 55?mv internal threshold. at startup or in case of extremely damped free oscillations, the zcd comparator may not be able to detect the valleys. to avoid such a situation, the NCL30085 features a time?out circuit that generates pulses if the voltage on zcd pin stays below the 55?mv threshold for 6.5 s. the time?out also acts as a substitute clock for the valley detection and simulates a missing valley in case the free oscillations are too damped. NCL30085 www. onsemi.com 21 figure 61. zero current detection block + ? zcd v zcd(th) time?out clock + ? v zcd(short) + ? s r q q aux_scp 90?ms timer 4?s timer (auto?recovery version) ff_mode t zcd(blank2) t zcd(blank1) t zcd(blank) vcc NCL30085 www. onsemi.com 23 protections the circuit incorporates a large variety of protections to make the led driver very rugged. among them, we can list: output short circuit situatio n an overload fault is detected if the zcd pin voltage remains below v zcd(short) for 90 ms. in such a situation, the circuit stops generating pulses until the 4?s delay auto?recovery time has elapsed (b version) or latches off (a version). winding or output diode short circuit protection if a transformer winding happens to be shorted, the primary inductance will collapse leading the current to ramp up in a very abrupt manner. the v ilim comparator (current limitation threshold) will trip to open the mosfet and eventually stop the current rise. however, because of the abnormally steep slope of the current, internal propagation delays and the mosfet turn?off time will make possible the current rise up to 50% or more of the nominal maximum value set by v ilim . as illustrated in figure 65, the circuit uses this current overshoot to detect a winding short circuit. the leading edge blanking (leb) time for short circuit protection (leb2) is significantly faster than the leb time for cycle?by?cycle protection (leb1). practically, if four consecutive switching periods lead the cs pin voltage to exceed (v cs(stop) =150% *v ilim ), the controller enters auto?recovery mode in version b (4?s operation interruption between active bursts) and latches off in version a. similarly, this function can also protect the power supply if the output diode is shorted or if the transformer simply saturates. figure 65. winding short circuit protection, max. peak current limit circuits s r q q cs leb1 + ? s r q q vcc aux vcc management vdd vccreset (grand reset) drv ipkmax pwmreset v ilimit + ? leb2 v cs(stop) wod_scp + ? stop sd pin ovp (ovp2) uvlo s r q q otp 4?s timer off latch latch 4?s timer vccreset 4?pulse counter aux_scp vcc(ovp) uvlo bonok tsd v control / 4 auto ? recovery (b version) latching ? off (a version) v cc over voltage protection the circuit stops generating pulses if v cc exceeds v cc(ovp) and enters auto?recovery mode. this feature protects the circuit if the output led string happens to open or is disconnected. programmable over voltage protection (ovp2) connect a zener diode between v cc and the sd pin to set a programmable v cc ovp (d z of figure 66). the triggering level is (v z +v ovp ) where v ovp is the 2.5?v internal threshold. if this protection trips, the NCL30085a latches off while the NCL30085b enters the auto?recovery mode. NCL30085 www. onsemi.com 24 figure 66. thermal foldback and ovp/otp circuitry s r q q grand reset sd vcc i otp(ref) + ? vdd + ? clamp rclamp vclamp latch otp(off) v / v ovp v ntc tf v s r q q 4?s timer off thermal foldback otp(start) t sd(delay) t otp(on) sd pin ovp (ovp2) detection otp detection z d NCL30085b (autorecovery version) ncp30085a (latching off version) the sd pin is clamped to about 1.35 v ( v clamp ) through a 1.6?k resistor ( r clamp ). it is then necessary to inject about v ovp v clamp r clamp that is 2.50 1.35 1.6 k 700 a typically, to trigger the ovp protection. this current helps ensure an accurate detection by using the zener diode far from its knee region . programmable over temperature foldback protection (otp) connect an ntc between the sd pin and ground to detect an over?temperature condition. in response to a high temperature (detected if v sd drops below v tf(start) ), the circuit gradually reduces the led current down 50% of its initial value when v sd reaches v tf(stop) , in accordance with the characteristic of figure 67 (note 9). if this thermal foldback cannot prevent the temperature from rising (testified by v sd drop below v otp ), the circuit latches off (a version) or enters auto?recovery mode (b version) and cannot resume operation until v sd exceeds v otp(on) to provide some temperature hysteresis (around 10 c typically). the otp thresholds nearly correspond to the following resistances of the ntc: ? thermal foldback starts when r ntc r tf(start) (11.7 k , typically) ? thermal foldback stops when r ntc r tf(stop) (8.0 k , typically) ? otp triggers when r ntc r otp(off) (5.9 k , typically) ? otp is removed when r ntc r otp(on) (8.0 k , typically) (note 10) 9. the above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum l evel if step?dimming is not engaged or a lower one based on the step?dimming value. 10. this condition is sufficient for operation recovery of the b version. for the a version which latches off when otp triggers, the circuit further needs to be reset by a v cc drop below v cc(reset) . NCL30085 www. onsemi.com 25 figure 67. output current reduction versus sd pin voltage at startup, when v cc reaches v cc(on) , the otp comparator is blanked for at least 180 s in order to allow the sd pin voltage to reach its nominal value if a filtering capacitor is connected to the sd pin. this avoids flickering of the led light during turn on. brown?out protection the NCL30085 prevents operation when the line voltage is too low for proper operation. as illustrated in figure 68, the circuit detects a brown?out situation if the v s pin remains below the v bo(off) threshold (0.9 v typical) for more than the 25?ms blanking time. in this case, the controller stops operating. operation resumes as soon as the v s pin voltage exceeds v bo(on) (1.0 v typical) and v cc is higher than v cc(on) . to ease recovery, the circuit overrides the v cc normal sequence (no need for v cc cycling down below v cc(off) ). instead, its consumption immediately reduces to i cc(start) so that v cc rapidly charges up to v cc(on) . once done, the circuit re?starts operating. + ? vs pin 1.0 v / 0.9 v 25?ms blanking time bonok figure 68. brown?out circuit die over temperature (tsd) the circuit stops operating if the junction temperature (t j ) exceeds 150 c typically. the controller remains off until t j goes below nearly 100 c. pin connection faults the circuit addresses most pin connection fault cases: ? cs pin short to ground the circuit senses the cs pin impedance every time it starts?up and after drv pulses terminated by the 36? s maximum on?time. if the measured impedance does not exceed 120 ohm typically, the circuit stops operating. in practice, it is recommended to place a minimum of 250?ohm in series between the cs pin and the current sense resistor to take into account possible parametric deviations. ? fault of the gnd connection if the gnd pin is properly connected, the supply current drawn from the positive terminal of the v cc capacitor, flows out of the gnd pin to return to the negative terminal of the v cc capacitor. if the gnd pin is not connected, the circuit esd diodes offer another return path. the accidental non?connection of the gnd pin is monitored by detecting that one of the esd diode is conducting. practically, the esd diode of cs pin is monitored. if such a fault is detected for 200 s, the circuit stops generating drv pulses. more generally, incorrect pin connection situations (open, grounded, shorted to adjacent pin) are covered by and9204/d . NCL30085 www. onsemi.com 26 fault modes the circuit turns off whenever a major faulty condition prevents it from operating: ? severe otp (v sd level below v otp(off) ) ? v cc ovp ? ovp2 (additional ovp provided by sd pin) ? output diode short circuit protection: ?wod_scp high? ? output / auxiliary winding short circuit protection: ?aux_scp high? ? die over temperature (tsd) in this mode, the drv pulses generation is interrupted. in the case of a latching?of f fault, the circuit stops pulsing until the led driver is unplugged and v cc drops below v cc(reset) . at that moment, the fault is cleared and the circuit could resume operation. in the auto?recovery case, the circuit cannot generate drv pulses for the auto?recovery 4?s delay. when this time has elapsed, the circuit recovers operation as soon as the v cc voltage has exceeded v cc(on) . in the b version, all these protections are auto?recovery. the sd pin otp and ovp, wod_scp and aux_scp are latching off in the a version (see table 6). table 6. protection modes aux_scp wod_scp sd pin otp sd pin ovp NCL30085a* latching off latching off latching off latching off NCL30085b auto?recovery auto?recovery auto?recovery auto?recovery ordering information device package type shipping NCL30085adr2g* soic?8 (pb?free/halide free) 2500/tape & reel NCL30085bdr2g soic?8 (pb?free/halide free) 2500/tape & reel *please contact local sales representative for availability NCL30085 www. onsemi.com 27 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCL30085/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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